Variable synthesisers for synthesising an output frequency from a reference frequency are extensively used where a range of selectable frequencies are required. Radio communications, and in particular, telecommunications are fields where variable frequency synthesisers are extensively used. Such variable frequency synthesisers may be direct frequency synthesisers or indirect frequency synthesisers. However, whether direct or indirect, all such frequency synthesisers include a frequency divider, which may be a dual divisor divider, or a multi-divisor programmable divider. In a dual divisor divider the divide by integer by which the divider divides the frequency varies between an integer value I and the integer value I+1. To divide the frequency passing through the divider by a rational number which includes an integer and a fraction, the divide by integer by which the frequency is divided is varied between the integer value I and the integer value I+1 over a series of divides. The average of the divides over a series of divides equals the rational number.
In a multi-divisor divider the divide by integer value of the divisor is varied through a number of integer values around the integer part of the rational number in order that over a series of divides, the average of the divides is equal to the rational number. Such dividers are controlled by a digital control signal which provides the varying values of the divide by integer of the divisor for the respective divisions. The fractional part of the rational number by which the frequency is to be divided is interpolated by an interpolator which provides the varying digital code for appropriately varying the value of the divide by integer for the respective divisions. A summer sums the varying digital code from the modulator with a digital code representing the integer value of the rational number and outputs the varying summed code. The digital output from the summer is applied to the control input of the divider for appropriately varying the integer value of the divisor for the respective divisions.
Such interpolators for interpolating the fractional part of a rational number by which the frequency through a multi-divisor programmable divider is to be divided are known. For example, U.S. Pat. No. 5,038,117 of Miller discloses an interpolator comprising a MASH cascade configured third order sigma-delta modulator. In the interpolator of Miller only the numerator of the fraction is selectable. Indeed, this is the case in virtually all known interpolators. The fact that only the numerator of the fraction is selectable in an interpolator leads to a number of disadvantages. For example, in the case of an indirect synthesiser which is implemented as a phase lock loop circuit, in which a dual or multi-divisor divider is located in the feedback loop, without complex mathematical computation for selecting integer values and the numerator values of rational numbers by which the feedback frequency is to be divided, it is not possible to provide series of selectable frequencies in steps of constant frequency between adjacent selectable frequencies, wherein different frequency series have different frequency step sizes, which are not integer related.
There are many applications where it is desirable to be able to provide selectable frequency series wherein the frequency step size between adjacent frequencies is easily variable from frequency series to frequency series. For example, in the field of mobile telecommunications two commonly used communication standards require that the selectable frequencies be stepped through frequency steps of different size. Under the GMS standard, communication is carried out in frequency channels around 900 MHz, but in frequency steps of 200 kHz, while under the IS-136 standard, communication is carried out in channels around 900 MHz, but in frequency steps of 30 kHz. Thus, it is desirable that a frequency synthesiser be provided which permits series of selectable frequencies to be selected in which the frequency step size between adjacent selectable frequencies is variable from series to series.
The transfer function of and indirect frequency synthesiser is       (          MI      +      F        )    Mwhere I is the integer of a rational number, F is the numerator and M is the denominator of a fractional part of the rational number by which the feedback frequency is to be divided. Thus, the output frequency from such an indirect frequency synthesiser is thus given by the equation       f    o    =                    MI        +        F            M        ⁢          f      r      where fo is the output frequency and fr is the reference frequency from which fo is being synthesised. Thus, if it were possible to selectively vary the denominator of the fractional part of a rational number by which the frequency is to be divided, series of selectable frequencies could be synthesised, in which the frequency step size between adjacent selectable frequencies could readily easily be varied from series to series.
U.S. Pat. No. 4,816,774 of Martin discloses a variable frequency synthesiser which includes a variable modulus interpolator which permits both the numerator and denominator of the fraction being interpolated to be selectively varied. However, in the interpolator of Martin, two accumulators are required for determining the varying digital code for providing varying values of divisor to the divider. The capacity of the two accumulators must be variable for accommodating selection of the denominator of the fraction. Such accumulators and their associated circuitry tend to be relatively complex, particularly when the capacity is other than a power of two, and furthermore, when implemented as an integrated circuit require significant die area compared to an accumulator of capacity fixed to a power of two. Additionally, an offset value is required to be calculated by trial and error in order to minimise the level of spurious responses for each frequency channel.
U.S. Pat. No. 4,965,531 of Riley also discloses an indirect frequency synthesiser which includes an interpolator for interpolating the fractional part of a rational number divider. The interpolator includes a sigma-delta modulator, and the denominator of the fraction part of the integer which is selectable is written into a positive register and a negative register. Depending on the output of the quantiser of the sigma-delta modulator, the positive or negative value of the denominator is selected and is returned in the negative feedback loop of the sigma-delta modulator for adding to the numerator of the fraction. The sigma-delta modulator is a second order sigma-delta modulator and includes a pair of series connected accumulators through which the summed value of the numerator and the denominator are passed. However, the sigma-delta modulator includes two integrators in a single feedback loop, and thus, tends to be unstable. In fact the interpolator of Riley is only stable when interpolating fractions where the numerator lies between minus half the denominator and plus half the denominator. Furthermore, if the interpolator of Riley is implemented with a sigma-delta modulator of higher order than second order, the range of numerator values within which the interpolator remains stable is further reduced. This imposes significant limitations on the variable modulus interpolator of Riley.
There is therefore a need for a variable modulus interpolator in which the numerator and the denominator of the fraction being interpolated by the interpolator are respectively selectable, and furthermore, which outputs a varying digital code for providing varying values of integer divisors corresponding to the fractional part of a rational number for applying to a control input to a multi-divisor frequency divider, or for other purposes, where it is required to interpolate a fraction into a varying digital code representative of the fraction.
The present invention is directed towards providing such a variable modulus interpolator. The invention is also directed towards providing a variable frequency synthesiser incorporating such a variable modulus interpolator.